Performance improvements of integrated circuits (ICs) are typically achieved by device miniaturization, and the device miniaturization concurrently results in increasing packaging density of the formed ICs. Methods and materials applied for interconnecting ICs are therefore becoming an increasingly more important part of forming packaged semiconductor devices.
The selection of materials (e.g. dielectrics and/or metals) used for the formation of the interconnect structure continue to be explored as a part of a continuing effort to improve device performance. An etch stop layer is usually disposed overlying conductive features (e.g. a conductive via) in a semiconductor structure such as the interconnect structure. However, the conventional material used to form the etch stop layer is not suitable for various conductive features due to poor adhesion between the etch stop layer and some of the materials (e.g. copper) of the conductive features. Therefore, there is a need to develop a semiconductor structure having an etch stop layer and a method of forming the same to tackle the problems.